As nonvolatile memory cells, may be mentioned, a split gate type memory cell and a stack gate type memory cell. The split gate type memory cell comprises two transistors of a memory MOS type transistor that constitutes a memory section, and a selection MOS type transistor for selecting its memory section to thereby fetch information therefrom. As a known document, there is known a technology described in 1994-Proceedings of IEEE, VLSI, Technology Symposium, pp 71-72. A structure and operation of a memory cell described therein will be explained in brief. This split gate type memory cell comprises a source, a drain, a floating gate and a control gate. As the injection of electrical charges into the floating gate, may be mentioned a source side injection system using the generation of hot electrons. The charges stored in the floating gate are ejected from a pointed end of the floating gate to the control gate. At this time, there is a need to apply a high voltage of 12 volts to the control gate. The control gate that functions as a charge ejection electrode, serves even as a gate electrode of a reading selection MOS type transistor. A gate oxide film for a selection MOS type transistor section is a deposited oxide film, which functions even as a film for electrically isolating the floating gate and a gate electrode of the selection MOS type transistor. As other known technologies related to the split gate type memory cell, there are known, for example, U.S. Pat. Nos. 4,659,828 and 5,408,115, Japanese Unexamined Patent Publication No. Hei 5(1993)-136422, etc.
The stack gate type memory cell comprises a source, a drain, and a floating gate and a control gate stacked on a channel forming region. The generation of hot electrons is used for the injection of electrical charges into the floating gate. The electrical charges stored in the floating gate are ejected toward a substrate. At this time, there is a need to apply a negative high voltage of −10 volts to the control gate. Reading is performed by applying a read voltage like 3.3 volts to the control gate. The stack gate type memory cell has been described in Japanese Unexamined Patent Publication No. Hei 11(1999)-232886, etc.
In terms of the speeding up of data processing, the speeding up of a read operation of a nonvolatile memory device becomes important even to the nonvolatile memory device. In the split gate type memory cell, the gate electrode of the selection MOS transistor is configured so as to function even as an erase electrode. Therefore, a gate insulating film had no other choice but to set its thickness to the same thickness as that of a write/erase-voltage control high-voltage MOS transistor in order to ensure a withstand voltage therefor. Thus, Gm (mutual conductance defined as current supply capacity) of the selection MOS transistor becomes small, so the split gate type memory cell is hardly a structure wherein a read current can be obtained sufficiently. If nothing is done, then the split gate type memory cell is not fit for a high-speed operation under a low voltage. Since a thick gate oxide film for realizing a high withstand voltage is adopted for the control gate to which a high voltage is applied upon write/erase operations, it reduces Gm at a read operation, so the stack gate type cell is hardly a structure wherein a read current can be ensured sufficiently.
U.S. Pat. Nos. 4,659,828 and 5,408,115 of the known documents respectively describe the invention related to the write/erase operations but do not refer to an improvement in the performance of the read operation. Further, although Japanese Unexamined Patent Publication No. Hei 5(1993)-136422 of the known document discloses a shape most analogous to that of the present invention, it shows the invention related to a method of insulating two gate electrodes adjacent to each other, and does not disclose read performance. A nonvolatile memory device unprovided for the prior art is needed which is adapted to a logical operation device brought to high performance.
A structure has been adopted wherein bit lines are hierarchized into main and sub bit lines, only a sub bit line connected with a memory cell to be operated and selected is selected and connected to its corresponding main bit line, and the parasitic capacity of the bit line by the memory cell is apparently reduced, whereby a high-speed read operation is realized. However, it has been found out by the present inventors that there is a fear that where it is necessary to apply a high voltage even to a bit line upon writing as in the stack gate type memory cell, a MOS transistor for selectively connecting a sub bit line to its corresponding main bit line must be brought to high withstanding, whereby Gm of a read path is further reduced and the speeding up by a hierarchized bit line structure based on the main/sub bit lines will not function sufficiently.
An object of the present invention is to eliminate a thick-film high-voltage MOS transistor that impairs speeding up, from a memory information read path.
Another object of the present invention is to provide a semiconductor device capable of reading memory information from a nonvolatile memory cell at high speed.
The above, other objects and novel features of the present invention will become apparent from the description of the present Specification and the accompanying drawings.